Chip Design

https://semiengineering.com/challenges-in-ramping-new-manufacturing-processes/

Despite a slowdown for Moore’s Law, there are more new manufacturing processes are rolling out faster than ever before. The challenge now is to decrease time to yield, which involves everything from TCAD and design technology co-optimization, to refinement of power, performance, area/cost, and process control and analytics. Srinivas Raghvendra, vice president of engineering at Synopsys, talks about the various steps involved in determining what can be printed on a wafer, how to reduce defect density, and what other concerns need to be addressed to ramp a new process.